1. Field of the Invention
The invention relates generally to the fabrication of integrated circuits. The invention relates more specifically to a method of forming a self-aligned interconnect structure on an integrated circuit chip where the interconnect structure extends through plural interconnection layers and optionally contacts a substrate contact region.
2. Cross Reference to Related Applications
The following copending U.S. patent applications are assigned to the assignee of the present applications, are related to the present application and their disclosures are incorporated herein by reference:
(A) Ser. No. 07/893,702 [Attorney Docket No. SMTI2004] filed Jun. 5, 1992 by Tatsuo Nakato et al. and entitled SILYLATED PHOTORESIST LAYER AND PLANARIZING METHOD.
(B) Ser. No. 07/922,983 [Attorney Docket No. SMTI2017] filed Jul. 28, 1992 by David A. Vidusek and entitled TRILAYER LITHOGRAPHIC PROCESS AND PRODUCTS THEREOF.
(C) Ser. No. 07/954,505 [Attorney Docket No. SMTI2018] filed Sep. 29, 1992 by David A. Vidusek and Hiroki Tabuchi and entitled LITHOGRAPHIC PROCESS FOR PRODUCING SMALL MASK APERTURES AND PRODUCTS THEREOF.
3. Description of the Related Art
Circuit points in an integrated circuit (IC) chip are often connected one to another by way of conductive lines defined in a plurality of interconnect layers.
In a conventional interconnect process, one or more to-be-contacted regions (such as the sources and/or drains of plural transistors) are first defined in the substrate.
A first oxide or other insulation layer is then formed over the to-be-contacted regions (sources/drains) and also over substrate regions that are not to-be contacted (e.g., channel regions of field effect transistors (FET's)).
Subsequently, a first photolithographic step is used to project a first "through-holes" pattern onto a temporary photoresist coating that is placed on the first oxide layer. The first pattern is developed to create a corresponding set of one or more vertical through-holes each extending through the first oxide layer to one of the to-be-contacted substrate regions (e.g., transistor sources/drains).
Then a first metal or other interconnect material (e.g. heavily doped polysilicon) is deposited onto the first oxide layer such that the deposited interconnect material (e.g., Metal-1 or Poly-1) defines a first interconnect layer, fills the through-holes in the process, and makes contact with the to-be-contacted substrate regions. The interconnect material that fills each vertical through-hole is referred to as an interconnect via.
Subsequently, a second photolithographic step is used to project a first "conductive-lines" pattern onto a temporary photoresist coating that is placed on the first interconnect layer (Metal-1 or Poly-1). The conductive-lines pattern is developed to create a corresponding set of one or more laterally extending conductive lines in the first interconnect layer (Metal-1 or Poly-1).
Next, a second oxide or other insulation layer is formed over the patterned first interconnect layer (e.g. Metal-1 or Poly-1) and a third photolithographic step is used to define and etch a second set of through-holes extending through the second oxide layer to the patterned first interconnect layer (e.g. to Metal-1 or Poly-1). This is followed by deposit and patterning of a second interconnect layer (e.g. Metal-2 or Poly-2), formation and etch-through of a third oxide layer, and so forth, until all interconnects have been made from one patterned interconnect layer to the next and to the to-be-contacted substrate region.
This conventional interconnect method suffers from several problems:
Problem (1): When an interconnection is to be made through multiple layers, it is often desirable to stack the patterned interconnect lines and corresponding vertical interconnect vias one directly above another so that overall consumption of lateral area over the chip surface will be minimized. Some leeway needs to be provided, however, for possible misalignment between the conductive-line patterns of successive interconnect layers and the through-hole patterns of successive oxide layers. This leads to design rules where interconnect vias are forced to have wider-than necessary diameters to assure that they will overlap with conductive lines above and below them even when worst case misalignment occurs. Spacings between laterally adjacent interconnect lines have to be enlarged in the region of the interconnect vias in order to avoid undesired shorts. Interconnect vias of multi-layer structures are conventionally staggered relative to one another in the lateral direction to avoid such problems and to assure that good contact is made between each vertical via and its respective top and bottom, laterally-extending conductor lines. As a consequence, the interconnect structures of IC chips are disadvantageously limited to having smaller densities (fewer vertical vias and/or conductive-lines per lateral square centimeter) than would otherwise be possible. The problem grows as more interconnect layers are added to a design because the worst case misalignment between plural interconnect layers is proportional to the number of layers.
Problem (2): Another problem of the conventional interconnect-forming approach is that multiple photolithographic steps are used to define a vertical series of through-holes. Each additional photolithographic step consumes more production time and increases the chance of process related defects. Production time and defect rates increase disadvantageously as more interconnect layers are added to a design.
Problem (3): Another shortcoming of the conventional interconnect-forming approach is that interconnect vias of that approach are limited to function only as high-conductivity elements.
There is a long felt and continuously increasing demand in the IC fabrication field for increasing the density at which interconnect and other functions are placed in each available two-dimensional lateral and/or three-dimensional space of an integrated circuit chip. Conventional integrated circuits have only two or three interconnect layers. One of the solutions proposed for increasing interconnect density and complexity is to provide four, five or even more interconnect layers on an IC chip. Unfortunately this is commercially impractical because of the above mentioned problems.